The structure of a conventional RF receiver used in a wireless communication system is illustrated in FIG. 1. As seen in the Figure, a received signal is input and transformed to I and Q (in-phase and quadrature) components in the receiver.
An important part of the receiver is the phase lock loop (PLL). The PLL is basically a closed loop frequency control system for purposes of synchronizing the phases of the two I and Q components together, thus determining the operational frequency of the receiver. The PLL function is based on the phase difference between the input and reference signals of a phase frequency detector (PFD). The PLL “locks” onto the phase of the reference signal so that the output signal of a voltage controlled oscillator (VCO) has a predefined phase relationship (for example, a zero, ninety or one hundred eighty degree relationship) with respect to the reference signal.
In general, it is desirable that the time for capturing the lock is as short as possible. Given that the PLL locking time is an important parameter in applications such as cellular radios where PLL locking times are critical, it is important that PLL locking times be verified. Thus, it would be beneficial in the art if a method were available that would allow for the easy measuring of PLL locking time accurately.
The receiver locking time is typically measured using automatic test equipment (ATE), such as an oscilloscope, to capture and image the control voltage of the PLL. The control voltage is output from an outside loop filter and then fed to the PLL to control the operation of the PLL. This prior art technique inherently suffers from a lack of indicating the phase of the control voltage (an oscilloscope generally only indicates amplitude), which reduces the overall accuracy of the resulting measurement.